2544 search results - page 301 / 509 » Process pipeline scheduling |
147
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GECCO
2009
Springer
15 years 11 months ago
2009
Springer
The paper deals with optimization of collective communications on multistage interconnection networks (MINs). In the experimental work, unidirectional MINs like Omega, Butterfly a...
151
Voted
CODES
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
120
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AGILEDC
2003
IEEE
15 years 10 months ago
2003
IEEE
: Before any of the current “agile” development methods, Earned Value Management provided information for planning and controlling complex projects by measuring how much “val...
162
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ICCAD
1999
IEEE
15 years 9 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
144
Voted
ASPDAC
2005
ACM
15 years 7 months ago
2005
ACM
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...