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FCCM
1999
IEEE
122views VLSI» more  FCCM 1999»
15 years 2 months ago
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
Andrew A. Chien, Jay H. Byun
79
Voted
SIGMOD
1999
ACM
127views Database» more  SIGMOD 1999»
15 years 2 months ago
An Adaptive Query Execution System for Data Integration
Query processing in data integration occurs over network-bound, autonomous data sources. This requires extensions to traditional optimization and execution techniques for three re...
Zachary G. Ives, Daniela Florescu, Marc Friedman, ...
103
Voted
HPCA
1998
IEEE
15 years 2 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
INFOCOM
1998
IEEE
15 years 2 months ago
Routing Lookups in Hardware at Memory Access Speeds
Increased bandwidth in the Internet puts great demands on network routers; for example, to route minimum sized Gigabit Ethernet packets, an IP router must process about packets pe...
Pankaj Gupta, Steven Lin, Nick McKeown
ICPP
1992
IEEE
15 years 2 months ago
Adaptive Binary Sorting Schemes and Associated Interconnection Networks
Many routing problems in parallel processing, such as concentration and permutation problems, can be cast as sorting problems. In this paper, we consider the problem of sorting on ...
Minze V. Chien, A. Yavuz Oruç