2544 search results - page 36 / 509 » Process pipeline scheduling |
95
Voted
EUROPAR
1997
Springer
15 years 1 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
ISCA
2003
IEEE
15 years 3 months ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
ISSS
1999
IEEE
15 years 1 months ago
1999
IEEE
Partition Scheduling with Prefetching (PSP) is a memory latency hiding technique which combines the loop pipelining technique with data prefetching. In PSP, the iteration space is...
NLPRS
2001
Springer
15 years 2 months ago
2001
Springer
The purpose of this study is to generate weather forecasts from XML-stored weather dataset. Reiter and Dale (2000) proposes Natural Language Generation (NLG) System as three-stage...
78
Voted
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...