2544 search results - page 53 / 509 » Process pipeline scheduling |
EUROPAR
2005
Springer
15 years 3 months ago
2005
Springer
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant ...
CASES
2007
ACM
15 years 1 months ago
2007
ACM
Delayed branching is a technique to alleviate branch hazards without expensive hardware branch prediction mechanisms. For VLIW processors with deep pipelines and many issue slots,...
131
click to vote
BMCBI
2008
14 years 9 months ago
2008
Background: Protein-amide proton hydrogen-deuterium exchange (HDX) is used to investigate protein conformation, conformational changes and surface binding sites for other molecule...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
- This paper introduces an innovative design which implements a high-performance JPEG-LS encoder. The encoding process follows the principles of the JPEG-LS lossless mode. The prop...
FCCM
2005
IEEE
15 years 3 months ago
2005
IEEE
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC’s 0.18μm CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic ...