2544 search results - page 59 / 509 » Process pipeline scheduling |
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
INFOCOM
2010
IEEE
14 years 8 months ago
2010
IEEE
Abstract—Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadeq...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...