Sciweavers

2544 search results - page 64 / 509
» Process pipeline scheduling
Sort
View
WIMOB
2008
IEEE
15 years 4 months ago
Proportional Fairness for MIMO Multi-user Schedulers with Traffic Arrival Process
—Packet scheduling at the data link layer may impact significantly the overall performance of a wireless system using multiple antennas. In this paper, we propose a novel packet ...
Masoomeh Torabzadeh, Wessam Ajib
ICDE
2010
IEEE
231views Database» more  ICDE 2010»
15 years 4 months ago
Estimating the progress of MapReduce pipelines
Abstract— In parallel query-processing environments, accurate, time-oriented progress indicators could provide much utility given that inter- and intra-query execution times can ...
Kristi Morton, Abram Friesen, Magdalena Balazinska...
ASPDAC
2008
ACM
69views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Fast, quasi-optimal, and pipelined instruction-set extensions
Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, th...
Ajay K. Verma, Philip Brisk, Paolo Ienne
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
14 years 10 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
HOTI
2002
IEEE
15 years 2 months ago
Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches
High-performance input-queued switches require highspeed scheduling algorithms while maintaining good performance. Various round-robin scheduling algorithms for Virtual Output Que...
Jing Liu, Chun Kit Hung, Mounir Hamdi, Chi-Ying Ts...