2544 search results - page 67 / 509 » Process pipeline scheduling |
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
BMCBI
2010
14 years 10 months ago
2010
Background: High-throughput automated sequencing has enabled an exponential growth rate of sequencing data. This requires increasing sequence quality and reliability in order to a...
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BMCBI
2004
14 years 9 months ago
2004
Background: All known genomes code for a large number of transcription factors. It is important to develop methods that will reveal how these transcription factors act on a genome...
CGO
2004
IEEE
15 years 1 months ago
2004
IEEE
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
FPGA
1995
ACM
15 years 1 months ago
1995
ACM
A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapat...