2544 search results - page 6 / 509 » Process pipeline scheduling |
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
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CF
2008
ACM
14 years 11 months ago
2008
ACM
To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi...
MEMOCODE
2007
IEEE
15 years 3 months ago
2007
IEEE
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
ISCAS
2002
IEEE
15 years 2 months ago
2002
IEEE
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
IPPS
1998
IEEE
15 years 1 months ago
1998
IEEE
In this paper, we propose an integrated approach for register-sensitive software pipelining. In this approach, the heuristics proposed in the stage scheduling method of Eichenberg...