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INFOCOM
2000
IEEE
15 years 2 months ago
Fast and Scalable Priority Queue Architecture for High-Speed Network Switches
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
Ranjita Bhagwan, Bill Lin
HPDC
2012
IEEE
13 years 5 days ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...
DATE
2009
IEEE
249views Hardware» more  DATE 2009»
15 years 4 months ago
White box performance analysis considering static non-preemptive software scheduling
—In this paper, a novel approach for integrating static non-preemptive software scheduling in formal bottom-up performance evaluation of embedded system models is described. The ...
Alexander Viehl, Michael Pressler, Oliver Bringman...
DATE
2010
IEEE
184views Hardware» more  DATE 2010»
15 years 2 months ago
Parallel subdivision surface rendering and animation on the Cell BE processor
—Subdivision Surfaces provide a compact way to describe a smooth surface using a mesh model. They are widely used in 3D animation and nearly all modern modeling programs support ...
R. Grottesi, S. Morigi, Martino Ruggiero, Luca Ben...
ACL
2006
14 years 11 months ago
Analysis and Repair of Name Tagger Errors
Name tagging is a critical early stage in many natural language processing pipelines. In this paper we analyze the types of errors produced by a tagger, distinguishing name classi...
Heng Ji, Ralph Grishman