Sciweavers

2544 search results - page 7 / 509
» Process pipeline scheduling
Sort
View
GLVLSI
1997
IEEE
110views VLSI» more  GLVLSI 1997»
15 years 1 months ago
Algorithm and Hardware Support for Branch Anticipation
Multi-dimensional systems containing nested loops are widely used to model scientific applications such as image processing, geophysical signal processing and fluid dynamics. Ho...
Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Pa...
RTAS
2008
IEEE
15 years 4 months ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
FPL
2009
Springer
135views Hardware» more  FPL 2009»
15 years 2 months ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
105
Voted
MICRO
1994
IEEE
124views Hardware» more  MICRO 1994»
15 years 1 months ago
A comparison of two pipeline organizations
We examine two pipeline structures which are employed in commercial microprocessors. The first is the load-use interlock (LUI) pipeline, which employs an interlock to ensure corre...
Michael Golden, Trevor N. Mudge
DAC
1993
ACM
15 years 1 months ago
Rotation Scheduling: A Loop Pipelining Algorithm
— We consider the resource-constrained scheduling of loops with interiteration dependencies. A loop is modeled as a data flow graph (DFG), where edges are labeled with the numbe...
Liang-Fang Chao, Andrea S. LaPaugh, Edwin Hsing-Me...