2544 search results - page 8 / 509 » Process pipeline scheduling |
ASAP
2000
IEEE
15 years 1 months ago
2000
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
IPPS
2002
IEEE
15 years 2 months ago
2002
IEEE
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
96
Voted
DATE
2005
IEEE
14 years 11 months ago
2005
IEEE
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
HPCA
1996
IEEE
15 years 1 months ago
1996
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
ICASSP
2011
IEEE
14 years 1 months ago
2011
IEEE
Current techniques used in pipelining recursive filters require significant hardware complexity. These techniques attempt to preserve the exact frequency response of the origina...