2544 search results - page 9 / 509 » Process pipeline scheduling |
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
EUROPAR
2006
Springer
15 years 1 months ago
2006
Springer
Single-dimension Software Pipelining (SSP) has been proposed as an effective software pipelining technique for multi-dimensional loops [16]. This paper introduces for the first tim...
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
PPL
2008
14 years 9 months ago
2008
The latency of broadcast/reduction operations has a significant impact on the performance of SIMD processors. This is especially true for associative programs, which make extensiv...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...