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» Processing-in-Memory: Exploring the Design Space
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DAC
2003
ACM
16 years 1 months ago
An IDF-based trace transformation method for communication refinement
In the Artemis project [13], design space exploration of embedded systems is provided by modeling application behavior and architectural performance constraints separately. Mappin...
Andy D. Pimentel, Cagkan Erbas
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 5 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 5 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
100
Voted
CORR
2010
Springer
142views Education» more  CORR 2010»
14 years 11 months ago
Budget Feasible Mechanisms
We study a novel class of mechanism design problems in which the outcomes are constrained by the payments. This basic class of mechanism design problems captures many common econom...
Christos H. Papadimitriou, Yaron Singer
112
Voted
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
14 years 10 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar