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» Processing-in-Memory: Exploring the Design Space
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DATE
2003
IEEE
98views Hardware» more  DATE 2003»
15 years 4 months ago
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as...
Abhik Roychoudhury, Tulika Mitra, S. R. Karri
ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
15 years 4 months ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 5 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
CASES
2006
ACM
15 years 4 months ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...
CODES
2005
IEEE
15 years 4 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra