707 search results - page 10 / 142 » Processor Architecture Design Using 3D Integration Technolog... |
DAC
2007
ACM
15 years 1 months ago
2007
ACM
This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a repl...
106
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ACMACE
2005
ACM
15 years 3 months ago
2005
ACM
Immersing players in believable and engaging virtual environments is a common goal for many interactive computer games. While PC-based audio only games set in virtual worlds have ...
113
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DAC
2010
ACM
14 years 8 months ago
2010
ACM
A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and an image signal process...
DAC
2012
ACM
13 years 4 days ago
2012
ACM
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...