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IPPS
2000
IEEE
15 years 2 months ago
Three Dimensional VLSI-Scale Interconnects
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
Dennis W. Prather
VR
2009
IEEE
319views Virtual Reality» more  VR 2009»
15 years 4 months ago
Virtual Heliodon: Spatially Augmented Reality for Architectural Daylighting Design
We present an application of interactive global illumination and spatially augmented reality to architectural daylight modeling that allows designers to explore alternative design...
Yu Sheng, Theodore C. Yapo, Christopher Young, Bar...
BMCBI
2007
167views more  BMCBI 2007»
14 years 9 months ago
MindSeer: a portable and extensible tool for visualization of structural and functional neuroimaging data
Background: Three-dimensional (3-D) visualization of multimodality neuroimaging data provides a powerful technique for viewing the relationship between structure and function. A n...
Eider B. Moore, Andrew V. Poliakov, Peter Lincoln,...
DAC
2000
ACM
15 years 10 months ago
Multiple Si layer ICs: motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...
ISJGP
2010
14 years 7 months ago
On the Hardware Implementation Cost of Crypto-Processors Architectures
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
Nicolas Sklavos