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FPL
2007
Springer
120views Hardware» more  FPL 2007»
15 years 4 months ago
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
Yohei Hasegawa, Hideharu Amano
DAC
2006
ACM
15 years 3 months ago
Design in reliability for communication designs
Silicon design implementation has become increasingly complex with the deep submicron technologies such as 90nm and below. It is common to see multiple processor cores, several ty...
Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar
ANSS
2000
IEEE
15 years 2 months ago
Using the DEVS Paradigm to Implement a Simulated Processor
This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of th...
Sergio Daicz, Alejandro Troccoli, Sergio Zlotnik, ...
ISCAS
2006
IEEE
103views Hardware» more  ISCAS 2006»
15 years 3 months ago
A low-power geometric mapping co-processor for high-speed graphics application
Abstract— In this article we present a novel design of a lowpower geometric mapping co-processor that can be used for high-performance graphics system. The processor can carry ou...
S. Leeke, L. Maharatna
RSP
2003
IEEE
103views Control Systems» more  RSP 2003»
15 years 3 months ago
An Instruction Throughput Model of Superscalar Processors
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
Tarek M. Taha, D. Scott Wills