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118
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NOCS
2007
IEEE
15 years 9 months ago
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
Paul Gratz, Karthikeyan Sankaralingam, Heather Han...
125
Voted
IEEESCC
2007
IEEE
15 years 9 months ago
Brave New Web: Emerging Design Principles and Technologies as Enablers of a Global SOA
Web Services have experienced great interest during the last years as they were expected to play a key role as enablers of seamless application-to-application integration both wit...
Christoph Schroth, Oliver Christ
102
Voted
DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 6 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
127
Voted
CODES
2008
IEEE
15 years 2 months ago
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
126
Voted
ARCS
2009
Springer
15 years 9 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...