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DAC
2007
ACM
15 years 10 months ago
Chip Multi-Processor Generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 2 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
ICSE
2005
IEEE-ACM
15 years 10 months ago
An architects guide to enterprise application integration with J2EE and .NET
Architects are faced with the problem of building enterprise scale information systems, with streamlined, automated internal business processes and web-enabled business functions,...
Ian Gorton, Anna Liu
ASPDAC
2004
ACM
104views Hardware» more  ASPDAC 2004»
15 years 3 months ago
A small-area high-performance 512-point 2-dimensional FFT single-chip processor
: A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multidatapath radix-23 computation el...
Naoto Miyamoto, Leo Karnan, Kazuyuki Maruo, Koji K...
ICS
1999
Tsinghua U.
15 years 2 months ago
Low-level router design and its impact on supercomputer system performance
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
Valentin Puente, José A. Gregorio, Cruz Izu...