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ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
15 years 4 months ago
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
Praveen Raghavan, José L. Ayala, David Atie...
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
15 years 2 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
IJSNET
2011
110views more  IJSNET 2011»
14 years 4 months ago
Sensor integration for perinatology research
— The numbers of high-risk pregnancies and premature births are increasing due to the steadily higher age at which women get pregnant. The long-term quality of life of the neonat...
Wei Chen, Jun Hu, Sibrecht Bouwstra, Sidarto Bamba...
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
15 years 2 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
EUROMICRO
2000
IEEE
15 years 2 months ago
A Simulink(c)-Based Approach to System Level Design and Architecture Selection
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
Luciano Lavagno, Begoña Pino, Leonardo Mari...