707 search results - page 4 / 142 » Processor Architecture Design Using 3D Integration Technolog... |
ISCA
2007
IEEE
15 years 4 months ago
2007
IEEE
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
SBACPAD
2007
IEEE
15 years 4 months ago
2007
IEEE
Multi-dimensional imaging techniques involve the processing of high resolution images commonly used in medical, civil and remote-sensing applications. A barrier commonly encounter...
ISCAS
2006
IEEE
2006
IEEE
Microelectromechanical systems in 3D SOI-CMOS: sensing electronics embedded in mechanical structures
15 years 3 months ago
— We discuss the design of CMOS MEMS in a 3D SOI-CMOS technology. We present layout architectures, preliminary mechanics modeling using finite element analysis and release proce...
ISQED
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...