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ISVLSI
2007
IEEE
204views VLSI» more  ISVLSI 2007»
15 years 4 months ago
Designing Memory Subsystems Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance ...
Mahmoud Ben Naser, Yao Guo, Csaba Andras Moritz
FCCM
2006
IEEE
101views VLSI» more  FCCM 2006»
15 years 3 months ago
A Type Architecture for Hybrid Micro-Parallel Computers
Recently, platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequenti...
Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
ICITA
2005
IEEE
15 years 3 months ago
DREAM: A Practical Product Line Engineering Using Model Driven Architecture
Both product line engineering (PLE) and model driven architecture (MDA) are emerging as effective paradigms for building a family of applications in cost effective way. PLE suppor...
Soo Dong Kim, Hyun Gi Min, Jin Sun Her, Soo Ho Cha...
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 3 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 2 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin