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DAC
2004
ACM
15 years 10 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
CASES
2001
ACM
15 years 1 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
WOSP
2005
ACM
15 years 3 months ago
Modeling the performance of a NAT/firewall network service for the IXP2400
The evolution towards IP-aware access networks creates the possibility (and, indeed, the desirability) of additional network services, like firewalling or NAT, integrated into th...
Tom Verdickt, Wim Van de Meerssche, Koert Vlaeminc...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 2 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ISCAPDCS
2007
14 years 11 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi