707 search results - page 5 / 142 » Processor Architecture Design Using 3D Integration Technolog... |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Extending 2-D planar topologies in integrated circuits (ICs) to a 3-D implementation has the obvious benefits of reducing the overall footprint and average interconnection length,...
3DIC
2009
IEEE
15 years 4 months ago
2009
IEEE
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
ICSE
2008
IEEE-ACM
15 years 10 months ago
2008
IEEE-ACM
The design and implementation of the reconstruction system in medical X-ray imaging is a challenging issue due to its immense computational demands. In order to ensure an efficien...
ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...