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ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
15 years 6 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
ISPASS
2007
IEEE
15 years 4 months ago
Modeling and Characterizing Power Variability in Multicore Architectures
Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors s...
Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ism...
VLSI
2012
Springer
13 years 5 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
DANCE
2002
IEEE
15 years 2 months ago
Active Network Monitoring and Control: The SENCOMM Architecture and Implementation
We present the architecture, design, and implementation of a Smart Environment for Network Control, Monitoring and Management (SENCOMM). SENCOMM uses active network technology to ...
Alden W. Jackson, James P. G. Sterbenz, Matthew Co...
FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
14 years 1 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...