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DAC
2008
ACM
15 years 11 months ago
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pa...
OTM
2010
Springer
14 years 8 months ago
Semantic Support for Computer-Human Interaction: Intuitive 3DVirtual Tools for Surface Deformation in CAD
Decision making is tightly related to the understanding of the design and manufacturing practices. In our previous work, we proposed an intuitive approach for geometric modeling in...
Ioana Ciuciu, Robert Meersman, Estelle Perrin, Fr&...
AAAI
2006
14 years 11 months ago
The Robot Intelligence Kernel
The Robot Intelligence Kernel (RIK) is a portable, reconfigurable suite of perceptual, behavioral, and cognitive capabilities that can be used across many different platforms, env...
David J. Bruemmer, Douglas A. Few, Miles C. Walton...
SPAA
2006
ACM
15 years 3 months ago
Modeling instruction placement on a spatial architecture
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
Martha Mercaldi, Steven Swanson, Andrew Petersen, ...
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
14 years 12 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...