Sciweavers

707 search results - page 8 / 142
» Processor Architecture Design Using 3D Integration Technolog...
Sort
View
CF
2009
ACM
15 years 4 months ago
Wave field synthesis for 3D audio: architectural prospectives
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
Dimitris Theodoropoulos, Catalin Bogdan Ciobanu, G...
ASPDAC
2012
ACM
238views Hardware» more  ASPDAC 2012»
13 years 5 months ago
Design for manufacturability and reliability for TSV-based 3D ICs
—The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technolog...
David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Mo...
ISCAS
2006
IEEE
152views Hardware» more  ISCAS 2006»
15 years 3 months ago
3D integrated sensors in silicon-on-sapphire CMOS
We fabricated a 3D-integrated multi-chip sensor separate dies [9]. In this paper, we present a 3D integrated and actuator and demonstrated the ability of communication with tempera...
Eugenio Culurciello, Andreas G. Andreou
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 4 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
14 years 7 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...