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» Processor Architectures for Ontogenesis
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DAC
2012
ACM
12 years 12 months ago
Self-aware computing in the Angstrom processor
Addressing the challenges of extreme scale computing requires holistic design of new programming models and systems that support those models. This paper discusses the Angstrom pr...
Henry Hoffmann, Jim Holt, George Kurian, Eric Lau,...
ACMSE
2011
ACM
13 years 9 months ago
Targeting FPGA-based processors for an implementation-driven compiler construction course
This paper describes the adaptation of a modern compiler construction course to target an FPGA-based hardware platform used throughout our computer science curriculum. One of the ...
D. Brian Larkins, William M. Jones
101
Voted
ASPLOS
2011
ACM
14 years 1 months ago
Inter-core prefetching for multicore processors using migrating helper threads
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
MICRO
2000
IEEE
88views Hardware» more  MICRO 2000»
14 years 9 months ago
Two-level hierarchical register file organization for VLIW processors
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
Javier Zalamea, Josep Llosa, Eduard Ayguadé...
FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
14 years 1 months ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...