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» Processor Architectures for Ontogenesis
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APCSAC
2003
IEEE
15 years 2 months ago
Towards an Asynchronous MIPS Processor
Qianyi Zhang, Georgios K. Theodoropoulos
SAMOS
2010
Springer
14 years 8 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
102
Voted
IPPS
2008
IEEE
15 years 3 months ago
DC-SIMD : Dynamic communication for SIMD processors
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Co...
74
Voted
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
15 years 3 months ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson