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» Processor Architectures for Ontogenesis
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IPPS
1994
IEEE
15 years 10 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
ASAP
2004
IEEE
126views Hardware» more  ASAP 2004»
15 years 10 months ago
Hyper-Programmable Architectures for Adaptable Networked Systems
We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in th...
Gordon J. Brebner, Philip James-Roxby, Eric Keller...
CASES
2001
ACM
15 years 10 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
CCGRID
2001
IEEE
15 years 10 months ago
A DSM Cluster Architecture Supporting Aggressive Computation in Active Networks
Active networks allow computations to be performed innetwork at routers as messages pass through them. Active networks offer unique opportunities to optimize networkcentric applic...
Peter C. J. Graham
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
15 years 9 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...