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» Processor Architectures for Ontogenesis
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JTRES
2010
ACM
15 years 6 months ago
WCET driven design space exploration of an object cache
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
Benedikt Huber, Wolfgang Puffitsch, Martin Schoebe...
ASPLOS
2008
ACM
15 years 8 months ago
Tapping into the fountain of CPUs: on operating system support for programmable devices
The constant race for faster and more powerful CPUs is drawing to a close. No longer is it feasible to significantly increase the speed of the CPU without paying a crushing penalt...
Yaron Weinsberg, Danny Dolev, Tal Anker, Muli Ben-...
MICRO
1999
IEEE
105views Hardware» more  MICRO 1999»
15 years 10 months ago
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
Todd M. Austin
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasa...
FTCS
1997
115views more  FTCS 1997»
15 years 7 months ago
Robust Emulation of Shared Memory Using Dynamic Quorum-Acknowledged Broadcasts
This paper presents robust emulation of multi-writer/multi-reader registers in message-passing systems using dynamic quorum con gurations. In addition to processor and link failur...
Nancy A. Lynch, Alexander A. Shvartsman