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» Processor Architectures for Ontogenesis
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FPL
2005
Springer
114views Hardware» more  FPL 2005»
15 years 11 months ago
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Buildi
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
Andy Gean Ye, Jonathan Rose
ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
15 years 11 months ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...
IEEEPACT
2003
IEEE
15 years 11 months ago
Memory Hierarchy Design for a Multiprocessor Look-up Engine
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal...
CSIE
2009
IEEE
15 years 10 months ago
K-Means on Commodity GPUs with CUDA
K-means algorithm is one of the most famous unsupervised clustering algorithms. Many theoretical improvements for the performance of original algorithms have been put forward, whi...
Hong-tao Bai, Li-li He, Dan-tong Ouyang, Zhan-shan...
LCPC
2001
Springer
15 years 10 months ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann