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» Processor Architectures for Ontogenesis
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ISCAS
2005
IEEE
99views Hardware» more  ISCAS 2005»
15 years 10 months ago
On the implementation of 128-pt FFT/IFFT for high-performance WPAN
- This paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in IEEE 802.15.3a standard. The 128-pt FFT/IFFT architecture has been designed by d...
C. Huggett, K. Maharatna, K. Paul
141
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ESTIMEDIA
2004
Springer
15 years 10 months ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu
CAV
2003
Springer
107views Hardware» more  CAV 2003»
15 years 10 months ago
Theorem Proving Using Lazy Proof Explication
Many verification problems reduce to proving the validity of formulas involving both propositional connectives and domain-specific functions and predicates. This paper presents ...
Cormac Flanagan, Rajeev Joshi, Xinming Ou, James B...
DELTA
2010
IEEE
15 years 10 months ago
Algorithm Transformation for FPGA Implementation
— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Donald G. Bailey, Christopher T. Johnston
IPPS
2000
IEEE
15 years 9 months ago
MAJC-5200: A High Performance Microprocessor for Multimedia Computing
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
Subramania Sudharsanan