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DAC
2006
ACM
16 years 6 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
VLSID
2002
IEEE
106views VLSI» more  VLSID 2002»
16 years 5 months ago
SWASAD: An ASIC Design for High Speed DNA Sequence Matching
This paper presents the Smith and Waterman Algorithm-Specific ASIC Design (SWASAD) project. This is a hardware solution that implements the S&W algorithm.. The SWASAD is an imp...
Tony Han, Sri Parameswaran
HPCA
2005
IEEE
16 years 5 months ago
Multithreaded Value Prediction
This paper introduces a novel technique which leverages value prediction and multithreading on a simultaneous multithreading processor to achieve higher performance in a single th...
Nathan Tuck, Dean M. Tullsen
HPCA
2004
IEEE
16 years 5 months ago
The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
Much research has been devoted to making microprocessors energy-efficient. However, little attention has been paid to multiprocessor environments where, due to the co-operative na...
Jian Li, José F. Martínez, Michael C...
AFRICACRYPT
2010
Springer
15 years 12 months ago
ECC2K-130 on Cell CPUs
This paper describes an implementation of Pollard’s rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband En...
Joppe W. Bos, Thorsten Kleinjung, Ruben Niederhage...