2700 search results - page 310 / 540 » Processor Architectures for Ontogenesis |
129
Voted
EH
1999
IEEE
15 years 9 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
145
click to vote
ICPPW
1999
IEEE
15 years 9 months ago
1999
IEEE
Group communication protocols are used in fault-tolerant systems to maintain strong replica consistency. The FaultTolerant Multicast Protocol (FTMP) described here is a group comm...
142
Voted
SIGGRAPH
1996
ACM
15 years 9 months ago
1996
ACM
The VC-1 is a parallel graphics machine for polygon rendering based on image composition. This paper describes the architecture of the VC-1 along with a parallel polygon rendering...
148
click to vote
ATS
2004
IEEE
15 years 8 months ago
2004
IEEE
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
139
click to vote
BIRTHDAY
2006
Springer
15 years 8 months ago
2006
Springer
We describe a gate level design of a FlexRay-like bus interface. An electronic control unit (ECU) is obtained by integrating this interface into the design of the verified VAMP pro...