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» Processor Architectures for Ontogenesis
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ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
15 years 7 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
EUROPDS
1997
15 years 6 months ago
A Combined Virtual Shared Memory and Network which Schedules
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
Ronald Moore, Bernd Klauer, Klaus Waldschmidt
ISCA
2006
IEEE
92views Hardware» more  ISCA 2006»
15 years 5 months ago
Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cr...
VLSISP
2008
159views more  VLSISP 2008»
15 years 4 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...
TVLSI
2008
164views more  TVLSI 2008»
15 years 4 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...