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» Processor Architectures for Ontogenesis
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MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
15 years 9 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
138
Voted
IWMM
2010
Springer
137views Hardware» more  IWMM 2010»
15 years 9 months ago
The locality of concurrent write barriers
Concurrent and incremental collectors require barriers to ensure correct synchronisation between mutator and collector. The overheads imposed by particular barriers on particular ...
Laurence Hellyer, Richard Jones, Antony L. Hosking
136
Voted
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 8 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
DAC
1995
ACM
15 years 8 months ago
Performance Analysis of Embedded Software Using Implicit Path Enumeration
—Embedded computer systems are characterized by the presence of a processor running application-specific dedicated software. A large number of these systems must satisfy real-ti...
Yau-Tsun Steven Li, Sharad Malik
CASES
2008
ACM
15 years 7 months ago
Dynamic coprocessor management for FPGA-enhanced compute platforms
Various commercial programmable compute platforms have their processor architecture enhanced with field-programmable gate arrays (FPGAs). In a common usage scenario, an applicatio...
Chen Huang, Frank Vahid