2700 search results - page 337 / 540 » Processor Architectures for Ontogenesis |
125
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DATE
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper explores the role of data analysis methods to support system-level designers in characterising the performance of embedded applications. In particular, we address the p...
154
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CODES
2000
IEEE
15 years 9 months ago
2000
IEEE
In this paper we present an approach to performance estimation for hard real-time systems. We consider architectures consisting of multiple processors. The scheduling policy is ba...
126
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DATE
2000
IEEE
15 years 9 months ago
2000
IEEE
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
126
Voted
IPPS
2000
IEEE
15 years 9 months ago
2000
IEEE
HeteroSort load balances and sorts within static or dynamic networks using a conceptual torus mesh. We ported HeteroSort to a 16-node Beowulf cluster with a central switch architec...
131
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EUROMICRO
1999
IEEE
15 years 9 months ago
1999
IEEE
The Komodo project concerns the handling of multiple real-time events by Java threads that are supported by a multithreaded Java microcontroller. The architecture of the processor...