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» Processor Architectures for Ontogenesis
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APCSAC
2006
IEEE
15 years 11 months ago
Issues and Support for Dynamic Register Allocation
Abstract. Post-link and dynamic optimizations have become important to achieve program performance. A major challenge in post-link and dynamic optimizations is the acquisition of r...
Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu
APCSAC
2006
IEEE
15 years 11 months ago
A Study of the Performance Potential for Dynamic Instruction Hints Selection
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
116
Voted
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
15 years 11 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...
DSD
2006
IEEE
116views Hardware» more  DSD 2006»
15 years 11 months ago
Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard
This paper addresses the implementation of ReedSolomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB...
Arjan C. Dam, Michel G. J. Lammertink, Kenneth C. ...
IPPS
2006
IEEE
15 years 11 months ago
Algorithmic skeletons for stream programming in embedded heterogeneous parallel image processing applications
Algorithmic skeletons can be used to write architecture independent programs, shielding application developers from the details of a parallel implementation. In this paper, we pre...
Wouter Caarls, Pieter P. Jonker, Henk Corporaal