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» Processor Architectures for Ontogenesis
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DATE
2003
IEEE
86views Hardware» more  DATE 2003»
15 years 10 months ago
Layered, Multi-Threaded, High-Level Performance Design
A primary goal of high-level modeling is to efficiently explore a broad design space, converging on an optimal or near-optimal system architecture before moving to a more detaile...
Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
EUROPAR
2003
Springer
15 years 10 months ago
A Parallel Algorithm for Incremental Compact Clustering
In this paper we propose a new parallel clustering algorithm based on the incremental construction of the compact sets of a collection of objects. This parallel algorithm is portab...
Reynaldo Gil-García, José Manuel Bad...
LCTRTS
2001
Springer
15 years 9 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
DAC
1999
ACM
15 years 9 months ago
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems
Power efficient design of real-time systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper ...
Youngsoo Shin, Kiyoung Choi
CODES
1998
IEEE
15 years 9 months ago
Communication synthesis and HW/SW integration for embedded system design
The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hardware accelerators) in one system. Interfacing hardwar...
Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pega...