2700 search results - page 370 / 540 » Processor Architectures for Ontogenesis |
142
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HPCA
2004
IEEE
16 years 4 months ago
2004
IEEE
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
125
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HPCA
2001
IEEE
16 years 4 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
138
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SIGMOD
2003
ACM
16 years 4 months ago
2003
ACM
Increasingly pervasive networks are leading towards a world where data is constantly in motion. In such a world, conventional techniques for query processing, which were developed...
117
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ICCAD
2005
IEEE
16 years 1 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
150
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RTAS
2009
IEEE
15 years 11 months ago
2009
IEEE
CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable environmen...