2700 search results - page 377 / 540 » Processor Architectures for Ontogenesis |
137
click to vote
HPCA
1999
IEEE
15 years 8 months ago
1999
IEEE
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
126
click to vote
IPPS
1999
IEEE
15 years 8 months ago
1999
IEEE
Clustering and scheduling of tasks for parallel implementation is a well researched problem. Several techniques have been presented in the literature to improve performance and re...
136
click to vote
ISCA
1999
IEEE
15 years 8 months ago
1999
IEEE
This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an instruction will produce th...
144
click to vote
ICS
1999
Tsinghua U.
15 years 8 months ago
1999
Tsinghua U.
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
122
click to vote
ISCA
1998
IEEE
15 years 8 months ago
1998
IEEE
Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these diffe...