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» Processor Architectures for Ontogenesis
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DATE
2009
IEEE
133views Hardware» more  DATE 2009»
15 years 11 months ago
SecBus: Operating System controlled hierarchical page-based memory bus protection
—This paper presents a new two-levels page-based memory bus protection scheme. A trusted Operating System drives a hardware cryptographic unit and manages security contexts for e...
Lifeng Su, Stephan Courcambeck, Pierre Guillemin, ...
SEUS
2009
IEEE
15 years 11 months ago
Towards Time-Predictable Data Caches for Chip-Multiprocessors
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
Martin Schoeberl, Wolfgang Puffitsch, Benedikt Hub...
INFOCOM
2009
IEEE
15 years 11 months ago
On the Impact of Heterogeneity and Back-End Scheduling in Load Balancing Designs
—Load balancing is a common approach for task assignment in distributed architectures. In this paper, we show that the degree of inefficiency in load balancing designs is highly...
Ho-Lin Chen, Jason R. Marden, Adam Wierman
DOLAP
2009
ACM
15 years 11 months ago
LMDQL: link-based and multidimensional query language
The current commercial and academic OLAP tools do not process XML data that make use of XLink. To develop OLAP systems for helping in the analysis of such data, this paper propose...
Paulo Caetano da Silva, Fábio Santos Souza,...
ARCS
2010
Springer
15 years 11 months ago
Exploiting Inactive Rename Slots for Detecting Soft Errors
Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical register mapping for...
Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, M...