In this paper various algorithms for sorting on processor networks are considered. We focus on meshes, but the results can be generalized easily to other decomposable architecture...
The appearance of 64-bit processors allows a new approach to microkernel desagn From our experience with a message passang microkernel MESHIX, we discovered that a multi-address s...
Kevin Murray, Tim Wilkinson, Tom Stiemerling, Paul...
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
The current main memory (DRAM) access speeds lag far behind CPU speeds. Cache memory, made of static RAM, is being used in today's architectures to bridge this gap. It provid...
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
Gary S. Tyson, Matthew K. Farrens, Andrew R. Plesz...