2700 search results - page 403 / 540 » Processor Architectures for Ontogenesis |
221
click to vote
VLSISP
2011
14 years 11 months ago
2011
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
164
click to vote
JODI
2010
14 years 11 months ago
2010
: ICE-TheOREM was a project which made several important contributions to the repository domain, promoting deposit by integrating the repository with authoring workflows and enhanc...
133
click to vote
TVCG
2010
14 years 11 months ago
2010
Abstract--One important bottleneck when visualizing large data sets is the data transfer between processor and memory. Cacheaware (CA) and cache-oblivious (CO) algorithms take into...
272
click to vote
GLVLSI
2011
IEEE
14 years 8 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
160
click to vote
HPCA
2011
IEEE
14 years 7 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...