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» Processor Architectures for Ontogenesis
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CODES
2009
IEEE
15 years 6 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
RTAS
2009
IEEE
15 years 6 months ago
Adaptive Failover for Real-Time Middleware with Passive Replication
Supporting uninterrupted services for distributed soft real-time applications is hard in resource-constrained and dynamic environments, where processor or process failures and sys...
Jaiganesh Balasubramanian, Sumant Tambe, Chenyang ...
ISCA
2009
IEEE
199views Hardware» more  ISCA 2009»
15 years 6 months ago
SigRace: signature-based data race detection
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
Abdullah Muzahid, Darío Suárez Graci...
MICRO
2009
IEEE
113views Hardware» more  MICRO 2009»
15 years 6 months ago
The BubbleWrap many-core: popping cores for sequential acceleration
Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly i...
Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas
MICRO
2009
IEEE
315views Hardware» more  MICRO 2009»
15 years 6 months ago
Control flow obfuscation with information flow tracking
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huan...