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» Processor Architectures for Ontogenesis
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JSA
2008
94views more  JSA 2008»
14 years 12 months ago
Energy reduction through crosstalk avoidance coding in networks on chip
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cri...
COMPUTING
2004
204views more  COMPUTING 2004»
14 years 11 months ago
Image Registration by a Regularized Gradient Flow. A Streaming Implementation in DX9 Graphics Hardware
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...
Robert Strzodka, Marc Droske, Martin Rumpf

Lecture Notes
1005views
17 years 1 days ago
Lectures on reconfigurable computing
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
Sherief Reda
ICDE
1999
IEEE
113views Database» more  ICDE 1999»
16 years 1 months ago
Parallel Algorithms for Computing Temporal Aggregates
The ability to model the temporal dimension is essential to many applications. Furthermore, the rate of increase in database size and response time requirements has outpaced advan...
Jose Alvin G. Gendrano, Bruce C. Huang, Jim M. Rod...
VIS
2004
IEEE
186views Visualization» more  VIS 2004»
16 years 1 months ago
Hardware-Accelerated Adaptive EWA Volume Splatting
We present a hardware-accelerated adaptive EWA volume splatting algorithm. EWA splatting combines a Gaussian reconstruction kernel with a low-pass image filter for high image qual...
Wei Chen, Liu Ren, Matthias Zwicker, Hanspeter Pfi...