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SIGSOFT
2008
ACM
16 years 19 days ago
A scalable technique for characterizing the usage of temporaries in framework-intensive Java applications
Framework-intensive applications (e.g., Web applications) heavily use temporary data structures, often resulting in performance bottlenecks. This paper presents an optimized blend...
Bruno Dufour, Barbara G. Ryder, Gary Sevitsky
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
16 years 15 days ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal
HPCA
2009
IEEE
16 years 13 days ago
Voltage emergency prediction: Using signatures to reduce operating margins
Inductive noise forces microprocessor designers to sacrifice performance in order to ensure correct and reliable operation of their designs. The possibility of wide fluctuations i...
Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. H...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 8 days ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 8 days ago
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions
In the automatic design of custom instruction set processors, there can be a very large set of potential custom instructions, from which a few instructions are required to be chos...
Nagaraju Pothineni, Anshul Kumar, Kolin Paul