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» Processor Architectures for Ontogenesis
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ICCD
2007
IEEE
151views Hardware» more  ICCD 2007»
15 years 8 months ago
Benchmarks and performance analysis of decimal floating-point applications
The IEEE P754 Draft Standard for Floating-point Arithmetic provides specifications for Decimal Floating-Point (DFP) formats and operations. Based on this standard, many developer...
Liang-Kai Wang, Charles Tsen, Michael J. Schulte, ...
ICCD
2004
IEEE
158views Hardware» more  ICCD 2004»
15 years 8 months ago
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Z...
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
15 years 8 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
ICCAD
2004
IEEE
100views Hardware» more  ICCAD 2004»
15 years 8 months ago
DynamoSim: a trace-based dynamically compiled instruction set simulator
Instruction set simulators are indispensable tools for the architectural exploration and verification of embedded systems. Different techniques have recently been proposed to spe...
Massimo Poncino, Jianwen Zhu
ICCAD
2001
IEEE
126views Hardware» more  ICCAD 2001»
15 years 8 months ago
Constraint Satisfaction for Relative Location Assignment and Scheduling
Tight data- and timing constraints are imposed by communication and multimedia applications. The architecture for the embedded processor imply resource constraints. Instead of ran...
Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Je...