2700 search results - page 461 / 540 » Processor Architectures for Ontogenesis |
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
Abstract—To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between...
DSN
2009
IEEE
15 years 6 months ago
2009
IEEE
Fault-tolerant architectures based on physical replication of components are vulnerable to faults that cause the same effect in all replica. Short outages in a power supply shared...
IEEEPACT
2009
IEEE
15 years 6 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
IISWC
2009
IEEE
15 years 6 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
BTW
2009
Springer
15 years 6 months ago
2009
Springer
Abstract: Green computing or energy saving when processing information is primarily considered a task of processor development. We, however, advocate that a holistic approach is ne...